1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including transistor elements having a double gate (FinFET) or triple gate architecture.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit elements that substantially determine performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a planar transistor architecture, on the distance between the source and drain regions, which is also referred to as channel length.
Presently, the vast majority of integrated circuits are based on silicon due to substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the past 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and thus allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a basic gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length for a planar transistor configuration requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although usage of high speed transistor elements having an extremely short channel may typically be restricted to high speed applications, whereas transistor elements with a longer channel may be used for less critical applications, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range or 1-2 nm that may not be compatible with requirements for performance-driven circuits.
Therefore, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has, therefore, been suggested to replace silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5) with a k of approximately 25, strontium titanium oxide (SrTiO3) having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
Although significant advantages may be obtained with respect to performance and controllability of sophisticated planar transistor architectures on the basis of the above-specified strategies, in view of further device scaling, new transistor configurations have been proposed in which a “three-dimensional” architecture may be provided in an attempt to obtain a desired channel width while at the same time maintaining good controllability of the current flow through the channel region. To this end, so-called FinFETS have been proposed in which a thin sliver or fin of silicon may be formed in a thin active layer of a silicon-on-insulator (SOI) substrate, wherein, on both sidewalls, a gate dielectric material and a gate electrode material may be provided, thereby realizing a double gate transistor, the channel region of which may be fully depleted. Typically, in sophisticated applications, the width of the silicon fins is on the order of 10 nm and the height thereof is on the order of 30 nm. In a modified version of the basic double gate transistor architecture, a gate dielectric material and a gate electrode may also be formed on a top surface of the fin, thereby realizing a tri-gate transistor architecture. With reference to FIGS. 1a-1b, the basic configuration of conventional FinFETS and characteristics associated with the conventional manufacturing techniques may be described in more detail.
FIG. 1a schematically illustrates a perspective view of a semiconductor device 100 which represents a conventional double gate or FinFET field effect transistor (FinFET) including a plurality of individual transistor cells 150. As illustrated, the device 100 comprises a substrate 101, such as a silicon substrate, having formed thereon a buried insulating layer, for instance in the form of a silicon dioxide material. Moreover, each of the transistor cells 150 comprises a Fin 110, which may represent a remaining portion of a silicon layer (not shown) initially formed on the buried oxide layer 102, thereby defining an SOI configuration. The Fin 110 comprises a portion 111 corresponding to drain and source regions and also a channel region (not shown) which is covered by a gate electrode structure 120, which may enclose a central portion of each of the Fins 110. That is, the gate electrode structure 120 may be formed on respective sidewalls 110A, 110B of the central part of each of the Fins 110 and may comprise an appropriate gate dielectric material, such as silicon dioxide, in combination with an electrode material, such as polycrystalline silicon. A top surface of the Fins 110 may be covered by a cap layer 112, which may be comprised of silicon nitride, silicon dioxide and the like. It should be appreciated that the cap layer 112 may also represent a gate dielectric material if, in addition to the sidewall surfaces 110A, 110B, the top surface of the Fins is also to be used as a channel region. The Fins 110 may have a height 110H, a width 110W and a length, i.e., an effective channel length that is substantially defined by the width of the gate electrode structure 120.
Typically, the semiconductor device 100 comprising the plurality of transistor cells 150 is formed by patterning the active silicon layer formed on the buried insulating layer 102 and performing appropriately designed manufacturing processes for providing the gate electrode structure 120. For example, the cap layer 112 may be formed in the active silicon layer, which may subsequently be patterned on the basis of sophisticated lithography and etch techniques in order to obtain the Fins 110. Thereafter, an appropriate gate dielectric material, such as silicon dioxide and the like, may be formed, for instance by oxidation and the like, followed by the deposition of an appropriate gate electrode material, such as polysilicon and the like. Next, the gate electrode structure 120 may be obtained by patterning the gate electrode material, for instance using well-established highly selective etch techniques, which are also well established for the manufacturing of polysilicon gate electrodes in planar transistor configurations. Thereafter, appropriate dopant profiles may be established for the drain and source regions 111, possibly in combination with appropriate spacer structures (not shown), which may be accomplished by corresponding ion implantation techniques.
FIG. 1b schematically illustrates a top view of the device 100 in a further advanced manufacturing stage. As illustrated, the drain regions of the individual transistor cells 150 and the corresponding source regions may be connected by an epitaxially re-grown silicon material, thereby forming a silicon layer 103 at the drain side and the source side, respectively. Typically, the silicon material at the drain side and the source side may be formed by selective epitaxial growth techniques, thereby requiring corresponding spacer elements 104 in order to provide a required offset of the material 103 with respect to the gate electrode material of the gate electrode structure 120. Depending on the overall process strategy, the spacer structures 104 may also be used for defining corresponding heavily doped drain and source areas after forming corresponding drain and source extension regions (not shown) with a reduced dopant concentration in order to appropriately connect to the corresponding channel regions formed on sidewalls of the central portions of the Fins 110. After forming the semiconductor material 103, thereby providing separate drain and source regions of the device 100, corresponding contact areas (not shown), for instance comprised of a metal silicide, may be formed in the semiconductor material 103 on the basis of well-established metal silicide process regimes. Thereafter, an appropriate contact structure may be formed by embedding the device 100 in an appropriate dielectric material and forming corresponding contact elements so as to connect to the drain and source regions 103 and the gate electrode structure 120 in accordance with the overall circuit configuration.
During operation, appropriate voltages may be applied to the device 100 in order to establish a current flow from drain to source when applying an appropriate control voltage to the gate electrode structure 120. Thus, a conductive channel may be created at the sidewalls of the Fins 110 that are covered by the gate electrode structure 120 wherein, depending on the overall device dimensions, a fully depleted semiconductor area may be gained within the Fin 110. It should be appreciated that, depending on the characteristics of the cap layer 112, the top surface of the Fins 110 covered by the gate electrode structure 120 may also act as a channel region, thereby providing an even further increased effective transistor width, while also enabling an increased height of the Fins 110 while still maintaining a substantially fully depleted state. Although the multiple gate transistor device 100 as illustrated in FIGS. 1a and 1b may be advantageous with respect to providing an increased drive current capability while still maintaining high controllability of the current flow between the drain and source areas 103, it turns out that a high degree of variability of device characteristics may occur, which is assumed to be caused, among other things, by the configuration of the common drain and source regions 103. For example, performing a silicidation procedure on the basis of the semiconductor layers 103, which have been epitaxially formed in an earlier manufacturing stage, may result in a certain degree of non-uniformity of the corresponding metal silicide regions with respect to the adjacent channel regions, which may thus contribute to a significant variability of the resulting overall drive current.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.